The present invention relates generally to amplifiers employing folded cascode topology, and more particularly to improved low noise, low quiescent current, low offset operational amplifiers having a large common mode input voltage range.
One of the most frequently used input-stage topologies which provides wide input common-mode range is the folded cascode arrangement, shown as a generalized block diagram in FIG. 1. The amplifier in FIG. 1 includes a pair of input transistors (not shown) in block 30, the base or gate of one input transistor being coupled to Vin− the base or gate of the other input transistor being coupled to Vin+. A tail current source I0 is coupled to the emitters or sources of the input transistors, and their collectors or drains are coupled to load resistors R1 and R2 and also to emitters or sources of a pair of cascode transistors (not shown), respectively, in block 31. The collectors or drains of the cascode transistors in block 31 are coupled by a load circuit 5 to VCC and to inputs of an output amplifier stage 9 which produces Vout. Compensation capacitor C1 is coupled between Vout and the (−) input of output stage 9, and compensation capacitor C2 is coupled between VEE and to the (+) input of output stage 9.
FIG. 2 shows a schematic diagram of a different and simpler amplifier configuration, in which the differential input transistor pair includes a pair of JFET input transistors J0 and J1 having their sources coupled to a tail current source I0 and their gates coupled to Vin− and Vin+, respectively. The drains of input transistors J0 and J1 are coupled to VEE through NPN active load transistors Q17 and Q18 and degeneration resistors R1 and R2 as shown. The drains of input transistors J0 and J1 are connected to bases of the input transistors Q12 and Q13, respectively, of a second amplifier stage. The emitters of transistors Q12 and Q13 are connected to a tail current source I3 and to the bases of active load transistors Q17 and Q18. The collectors of transistors Q12 and Q13 are coupled to an active load circuit Q14, Q15 of the second amplifier stage. A compensation capacitor C1 is coupled between the base and collector of transistor Q13, and compensation capacitor C2 is connected between the base of transistor Q12 and VEE.
In the simpler differential pair topology shown in FIG. 2, the slew rate is determined simply by the magnitude of the tail current I0 and the size of the compensation capacitor C1.
However, in the more complex folded cascode topology of FIG. 1, the slew rate is determined not only by the magnitude of the tail current source I0 and the size of the compensation capacitor C1, but is additionally determined by the amount of current flowing through the cascode transistors in block 31.
Thus, when comparing the folded cascode topology of FIG. 1 to a simple differential pair topology as shown in FIG. 2, it can be seen that the folded cascode topology will need to have higher quiescent current to achieve comparable slewing performance.
In order to make the slew rate of an operational amplifier having the folded cascode circuitry of FIG. 1 comparable to the slew rate of a second stage or output stage that has the simple differential input pair Q12,Q13 in FIG. 2, the cascoding transistors in block 31 of FIG. 1 must conduct the same amount of current as the input pair transistors in block 30 of FIG. 1. Unfortunately, this not only causes higher quiescent current in the folded cascode amplifier in FIG. 1, but also approximately doubles the amount of current flowing into load resistors R1 and R2, and therefore approximately doubles the voltage drop across them. Consequently, the common mode input voltage range is substantially reduced in the folded cascode amplifier of FIG. 1 if it is designed to have slewing performance comparable to that of the simpler differential pair topology of FIG. 2.
As a practical matter, the resistances of load resistors R1 and R2 in the folded cascode amplifier of FIG. 1 cannot be substantially reduced because that would increase the folded cascode stage transconductance Gm presented to the cascoding transistors in block 31, which in turn would increase its noise and offset noise contribution. (It should be noted that folded cascode topology can also be implemented using current sources in place of resistors R1 and R2 in FIG. 1. However, although the cascode transistors in block 31 of FIG. 1 can be degenerated by very high output resistances of those current sources, in practice such current sources themselves become noise and offset contributors.)
In order to minimize the quiescent current and the noise contribution of the folded cascode transistors in block 31 of FIG. 1, the amount of current flowing through the folded cascode transistors can be reduced. Furthermore, decreasing the quiescent current through the cascode transistors in block 31 increases the output resistance of the folded cascode stage and that, in turn, increases the voltage gain of the amplifier. The improved voltage gain is useful to minimize the noise and offset voltage contributions of any following stages (if present) when the noise and offset voltage contributions are referred back to the input terminals of the pair of input transistors in block 30. Unfortunately, reducing the quiescent current through the folded cascode transistors in block 31 of FIG. 1 reduces the slew rate of the folded cascode amplifier, as explained above.
There are known “slew boost” techniques for improving slew rate when quiescent current in the folded cascode stage is reduced. However, the known slew boost techniques use nonlinear types of slew boost circuits that boost the current flowing through the folded cascode stage or bypassing it. However, employing a nonlinear slew boost circuit in an amplifier results in additional signal distortion.
There is an unmet need for a low noise, low offset operational amplifier which has improved common mode input voltage range and high slew rates.
There also is an unmet need for an operational amplifier using folded cascode topology with the folded cascode stage running lower current than the differential input stage for improved noise and offset performance and/or wider common mode input voltage range while providing slew rate performance determined by a full amount of output current of the differential input transistor pair, without substantial degradation of linearity when the operational amplifier approaches a slewing condition.